The trend in semiconductor manufacture continues to be reducing the size of semiconductor devices while, at the same time, increasing their density on the chip. From a performance standpoint, the trend is to increase the speed of the devices and to reduce their power consumption. At the present time, the integrated circuit chips consist of billions of devices on each chip.
To be able to reduce the size and density of the devices on the chip, the dimensions of the devices have to be made small. For example, the dimensions of the gate thickness and the source and drain of the FET now are in the micrometer and nanometer range. With these miniature dimensions, however, performance problems of the devices result, such as short channel effects, punch through, and current leakage.
One solution to these performance problems is to embed strained regions of, for example, eSiGe in pFET (compressive strain/stress for hole mobility enhancements) and, for example, eSiC in nFET (tensile strain/stress for electron mobility enhancements), preferably by a low to high temperature epitaxy process, after first forming recesses in a substrate for the eSiGe and eSiC. These embedded strained regions, which are in the substrate on either side of the channel region, are generally aligned to the gate of the FET and are doped in the same manner as the regular source/drain regions of the FETs. The embedded strained regions function mainly to create a respective stress/strain (compressive strain/stress for pFETS and tensile strain/stress for nFETs) in the channel to increase carrier mobilities.
Preferably, the eSiGe and eSiC are epitaxially deposited in the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of the silicon. The large spacing creates a stress (compression) in the channel of the transistor between the source and the drain layers. Due to the inclusion of the carbon, the lattice of the alloy has a smaller spacing than the spacing of the lattice of the layer of the silicon. The smaller spacing creates a stress (tensile) in the channel of the transistor between the source and drain layers. The stresses (compressive due to eSiGe for pFET or PMOS and tensile due to eSiC for nFET or NMOS) together with reduced resistivity due to the higher active dopant concentration, increases carrier mobility or Idsat and Idlin of the transistor, such as CMOS.
In order for a FET transistor, such as a CMOS, to work properly, various dopants, including halo, extension, and source/drain, need to be implanted at the right places and with specific concentrations. The implantation of all of these various dopants into the embedded strained layers (i.e., —eSiGe and eSiC) generate a great amount of damage into the strained layers. Damage relaxes the strained silicon (which is believed to be due to displacing the substitution strained dopants to the interstitial site which, in turn, reduces the strain/stress in the embedded strained eSiGe and eSiC layers in the source/drain regions and also further believed that strained silicon may experience relaxation via misfit/threading dislocation propagation). This relaxation caused by implanted doping damage from the halo, extension and source/drain implantations into the embedded strained layers reduces the strain/stress in the embedded strained layers, which, in turn, reduces the strain/stress in the channel which, in turn, reduces the carrier mobility and degrades the device performance. Various stress measurement data shows that approximately more than 50% of stress relaxes just after the halo implantation itself into the embedded strained eSiGe and eSiC layers in the source/drain regions. Further additional strain relaxation occurs (additional 10 to 20%) by performing the extension implantation into the embedded strained source/drain regions. Another additional 10 to 20% strain/stress relaxation occurs after the source/drain implantation into the embedded strained source/drain regions.
This strain relaxation causes a reduction of stress/strain in the source/drain embedded strain layers. This creates a performance problem because the embedded strain layers in the source/drain region stress the channel and then create the respective strain/stress in the channel for carrier mobility. However, the reduced source/drain stress causes reduction of channel stress and the reduced strain/stress in the channel, in turn, degrades the device performance because strain/stress in the channel is directly proportional to carrier mobility.